This invention relates to high-speed serial interface (“HSSI”) circuitry in programmable logic devices (“PLDs”). More particularly, this invention relates to an apparatus and method for correlating data samples received in a HSSI block with status signals generated by one or more first-in first-out (“FIFO”) buffers in the HSSI block. Although the invention is described herein primarily in the context of HSSI being implemented in PLDs for clarity, the invention may be applied to other suitable types of communication protocols being implemented in other suitable types of devices.
HSSI is a commonly-used communications interface that is used in a variety of communications applications. For example, HSSI may be implemented in PLDs in order to provide a high-speed interface between the PLD and an external device, such as an application specific integrated circuit (“ASIC”), application specific standard product (“ASSP”) or another PLD.
To compensate for potential clock domain differences in a HSSI data stream that is transmitted between two devices, idle characters (one type of “control” character that is transmitted) are typically periodically inserted into the data stream in accordance with most HSSI protocols. Furthermore, the HSSI circuitry typically includes memory elements such as FIFO buffers that store the individual data samples as they are transmitted from one device to the other. Subsequently, whenever data is transmitted faster than the rate at which the data is received, the FIFO buffers may effectively increase the rate at which data is received without losing data by dropping the idle characters from the data stream. On the other hand, the presence of the idle characters increases the rate of the data stream. Nevertheless, when the data is transmitted slower than the rate at which the data is received, the HSSI circuitry may stop transmitting the data stored in the FIFO buffers and instead revert to sending a stream of idle characters to the receiving device, matching the receiving data rate and avoiding a disruption in downstream processing.
Thus, it is seen that the operation of the HSSI circuitry described above typically occurs whenever the level of the FIFO buffer—that indicates how full or how empty the FIFO buffer is—exceeds a threshold (i.e., beyond which the FIFO buffer is “at risk” of becoming full or empty). Such threshold levels may, for instance, be specified by the user or configured by the manufacturer. For example, a FIFO buffer may be considered to be at risk of becoming full when it can only store two more data samples. Similarly, a FIFO buffer may be considered to be at risk of becoming empty when there are only two data samples left in the FIFO buffer.
In addition to monitoring how full or empty a FIFO buffer is for the purpose of deleting or adding idle characters, a FIFO buffer in the HSSI circuitry of a PLD, for example, also transmits status signals to the PLD that indicate how full or empty the FIFO buffer is. These status signals are typically transmitted on a dedicated status line directly from a particular FIFO buffer to the PLD as soon as, or shortly after, the status signals are generated. As a result, the status signals are generally uncorrelated with the transmission of the incoming data samples.
In designing the PLD to support the processing of HSSI data, users typically design the PLD to stop processing when the received data samples correspond to idle characters (known as an “idle sequence”) and to resume processing when the received data samples correspond to actual, valid data. To accomplish this, a determination is made as to whether a received data sample corresponds to a valid data sample or an idle character.
In one approach, logic can be designed using programmable logic resources referred to as logic elements (“LEs”) in the PLD to detect the transmission of idle characters in the HSSI data stream. However, this approach has several drawbacks, including the additional consumption of LEs in the PLD (which may cause customers to order larger PLDs and thereby incur additional costs), slower PLD performance, and added design time.
In another approach, the FIFO buffer status signals can be correlated with the data samples by measuring and adjusting the latency between the incoming data samples and the corresponding FIFO status signals. Software may be used to compute such latency. Although this approach does not require logic to detect an idle sequence, correlating the FIFO status signals to the data samples is difficult. For instance, the latency of a data sample that is transmitted from an external device to a PLD varies according to a PLD clock frequency that is set by a user. Furthermore, if different bits of a given data sample are transmitted in different physical datapaths, the latency of each datapath needs to be taken into consideration. Because calculating the latency for such signals depends on different factors including the physical routing of the signals (i.e., the datapaths), PLD clock speed, PLD layout, and the process parameters of the PLD, it is difficult to accurately calculate these latencies in order to correlate the FIFO status signals with the data samples.
Accordingly, it would be desirable to provide a more accurate and efficient apparatus and method for correlating data samples and FIFO status signals in a PLD.